Responsibilites: Lead Co-Design from Silicon to System- Partner with silicon design, Business Units, customers, and package architecture teams to define new product concepts from the earliest stages of chip development- Optimize die floorplans, interconnection schemes, and package architectures — from concept to HVM- Drive trade-off studies and architecture decisions for advanced DRAM products targeting AI/Data Center, Mobile, Automotive, and Edge Computing applicationsOwn Package Layout and Architecture- Lead floorplanning, high-density routing, placement, and package layout for advanced memory packages- Define and optimize substrate stack-ups, wire bond and flip chip interconnect schemes, and BEOL/RDL flows- Create wire bond diagrams, interposer drawings, and complete manufacturing documentation packagesDrive Electrical and Physical Design Quality- Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation results into design decisions- Conduct DFM reviews and feasibility studies; interpret parasitic modeling and validation data- Drive material selection decisions based on simulation, reliability, and manufacturability dataCollaborate Globally to Scale and Sustain- Partner with OSAT assembly partners, substrate suppliers, and Technology Development teams to define design rules and advance routing methodologies for next-gen solutions- Lead DFMEA reviews and define assembly DOEs to ensure HVM readiness- Support continuous improvement: global design alignment, IP development, competitive analysis, and package design roadmaps Minimum Qualifications - Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field + 5 years of semiconductor package design experience- OR Master's degree in the above fields + 3 years of semiconductor package design experience- Hands-on proficiency with advanced package EDA tools such as Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, or Siemens/Mentor Xpedition- Experience with flip chip, wire bond interconnects, BEOL/RDL flows, substrate stack-ups, and high-density routing- Experience partnering with SI/PI simulation teams to drive package architecture and design optimization- Experience collaborating with OSAT partners or assembly engineering organizations to deliver designs through HVM Preferred Qualifications 7 plus years of proven experience with advanced DRAM technologies — LPDDR, HBM, or GDDR- Experience with TSV stacking, micro-bump layout, and Chip-Package Interaction (CPI) analysis- Familiarity with 2.5D/3D-IC, Fan-Out Wafer Level Packaging (FOWLP), and System-in-Package (SiP)- Experience with Assembly DOE definition, DFMEA reviews, and process/material development in HVM- Proficiency with AutoCAD / Autodesk Mechanical for package and interposer drawings- Experience leading co-design engagements and silicon floorplan optimization. This is a high-impact, highly visible role where you'll work across the full product lifecycle — from early-stage co-design with silicon teams all the way to High Volume Manufacturing (HVM).If you thrive where precision meets innovation, where your decisions shape products reaching millions of users worldwide, and where your expertise directly influences how the AI era unfolds — this role is for you!