Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital). As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.