Product Design Engineer II Pinnacle Technical ResourcesProduct Design Engineer IICupertino,, California$50–$60 / hourContractorThe specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Client’s approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials.
Flexible Packaging Engineer - Destiny Packaging |Salinas, CA Bunzl plcFlexible Packaging Engineer - Destiny Packaging |Salinas, CASalinas, CAUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. Experience with MAP, barrier films, laminated structures, COEX films, SUPs, flexo print, shrink, stretch, and poly bag structures is preferred.
Senior IC Packaging Engineer Axiado CorpSenior IC Packaging EngineerSan Jose, CAAxiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Companys 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliances 2025 Start-Up to Watch award. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.
Senior Packaging Engineer Zp Group LlcSenior Packaging EngineerSaratoga, CA$210,000–$265,000 / yearKeywords: advanced packaging, flip‑chip, multi‑chip module, MCM, organic substrate, CoWoS, 2.5D, 3D packaging, TSMC system‑on‑wafer, OSAT, Wistron, module integration, cold plate integration, wafer‑level assembly, substrate technology, semiconductor packaging, high‑density interconnect, HDI substrates, yield improvement, semiconductor manufacturing, module engineering. The ideal Senior Packaging Engineer will lead advanced component and system‑level packaging efforts, with a strong emphasis on pcb assembly and organic substrate technologies on site in Saratoga, CA.
NewStaff IC Packaging Engineer - Advanced Packages & Power Analog DevicesStaff IC Packaging Engineer - Advanced Packages & PowerSan Jose, CAAnalog Devices, Inc. is searching for a highly motivated Staff Semi Packaging Engineer based in San Jose, CA. The position focuses on advanced IC package platforms, project management, and collaboration with cross-functional teams.
Photonic Packaging Engineer, Principal Astera Labs IncPhotonic Packaging Engineer, PrincipalSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
NewFlexible Packaging Engineer Destiny Packaging Inc.Flexible Packaging EngineerSalinas, CAPart timeUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. Experience with MAP, barrier films, laminated structures, COEX films, SUPs, flexo print, shrink, stretch, and poly bag structures is preferred.
NewPackaging Engineer Analog DevicesPackaging EngineerSan Jose, CA$86,480–$118,910 / yearPackage-level and system-level thermal/mechanical/electrical/magnetic simulation skill is a plus.*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers.
NewPackaging Engineer: IC & Power Module Design Analog DevicesPackaging Engineer: IC & Power Module DesignSan Jose, CA$86,480–$118,910 / yearA Bachelor's degree in Materials Science, Electrical Engineering, or related fields is required, along with knowledge in IC design, data analysis, and programming in Python. Analog Devices, Inc. seeks a Packaging Engineer in San Jose, CA, to design and optimize IC packages for diverse products.
Staff Semi Packaging Engineer Analog DevicesStaff Semi Packaging EngineerSan Jose, CaliforniaADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.
NewSenior IC Packaging Engineer - NPI & HVM Leadership Broadcom CorporationSenior IC Packaging Engineer - NPI & HVM LeadershipSan Jose, CAWith a strong educational background in engineering and extensive hands-on experience in advanced IC packaging, you will manage packaging deliverables, ensuring optimal design and execution throughout the lifecycle.#J-18808-Ljbffr. You'll collaborate closely with chip design, system design, and manufacturing teams to deliver industry-leading package solutions.
NewSenior Substrate & 3DIC Packaging Engineer TSMC - Taiwan Semiconductor Manufacturing Company LimitedSenior Substrate & 3DIC Packaging EngineerSan Jose, CAA leading semiconductor foundry in San Jose seeks a highly skilled Substrate / Advanced Package Engineer to innovate in 3DIC design and packaging. Responsibilities include designing, simulating, and optimizing advanced packaging technologies while collaborating with cross-functional teams.
Flexible Packaging Engineer BUNZLFlexible Packaging EngineerSalinas, CA$75,000–$80,000 / yearUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. With more than 10,000 team members and over 400,000 supplies, Bunzl is recognized as a leading supplier across North America—and proudly certified as a Great Place to Work® .
Silicon Photonics & Optical Packaging Engineer Apple IncSilicon Photonics & Optical Packaging EngineerCAIn this highly visible role, you will develop Si photonics engine/chiplet packaging and co-packaging solutions utilizing advanced packaging technologies, define assembly baseline processes, decide package BOM, establish optical coupling design/manufacturing that are optimized for performance, reliability, yield and cost. Si photonics based optical engine package architecture / Package integration and drive micro-optical component assembly/interface characterization through Innovation Work with optical component vendors, foundry and OSAT to bring Si photonics packaging solution from concept to HVM.
Senior Engineer, Semi Packaging Engineering Analog DevicesSenior Engineer, Semi Packaging EngineeringSan Jose, CaliforniaRequirements: Must have a Master’s degree in Mechanical Engineering, Materials Science, Electrical Engineering, Autonomy and Robotics Engineering, or related field (willing to accept a foreign education equivalent) and two (2) years of experience as a Packaging Engineer or related occupation conceptualizing and productizing semiconductor devices to bridge analog signals to digital Cloud. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.
Integrated Circuit - Packaging Architect Engineer Advanced Micro Devices, IncIntegrated Circuit - Packaging Architect EngineerSan Jose, CaliforniaSuccessful candidate would collaborate with product design teams and technology development partners to understand future product needs and define a packaging roadmap that includes architecture, process definition, Design for Manufacturing (DFM) and Design for Yield (DFY) guidelines. Responsibilities: The Role : Advanced packaging technology leader driving packaging architecture across client, server, gaming and GPU products.
Software Engineer 5 - Ads Pricing & Packaging Netflix IncSoftware Engineer 5 - Ads Pricing & PackagingLos Gatos, CA$388,000–$619,000 / yearThe Ads Pricing and Packaging team is responsible for developing cutting-edge inventory management systems which support various monetization strategies, including dynamic pricing, rate card management, product packaging, inventory segmentation, and yield optimization. Skills & experience we're seeking: Professional experience in building inventory management solutions that support monetization strategies such as dynamic pricing, rate card management, product packaging, inventory split and yield management.
Packaging Assembly Engineer Apple IncPackaging Assembly EngineerCupertino, CAIn this highly visible role, you will own development, optimization and sustaining the advanced flip-chip BGA (FCBGA) assembly process from pathfinding, NPI through high-volume manufacturing by defining assembly baseline processes, deciding package BOM, establishing package design rules that are optimized for performance, reliability, yield and cost for a variety of projects including SoC. Define and optimize end-to-end FCBGA assembly process flow (wafer back-end interface, flip-chip attach, underfill, lid/heat spreader attach, ball attach, singulation, final inspection).
Packaging Product Design Engineer Apple IncPackaging Product Design EngineerCupertino, CACollaborate with cross-functional teams including industrial design, hardware, environmental, operations, and technology groups to refine and execute on the design on the packaging. Apple's approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials.
Semiconductor Packaging Modeling and Simulation Engineer onsemiSemiconductor Packaging Modeling and Simulation EngineerSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. As a semiconductor packaging modeling and simulation engineer, you will have the opportunities to support new power module development and new product design, assembly and process, quality and reliability, and customers in worldwide.
Packaging Product Design Engineering Manager Apple IncPackaging Product Design Engineering ManagerCupertino, CAApple's approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials. As a Packaging PD Manager, you will lead a team of engineers to design and execute packaging architecture from initial prototypes to mass production with sustainable packaging material.
Cloud Hardware Development, Packaging, Network Product Development - Optics Amazon.com IncCloud Hardware Development, Packaging, Network Product Development - OpticsCupertino, CAYou will perform high-quality design, development, validation, and sustaining engineering of IC and SOC packages for high-speed applications, working closely with design teams, manufacturing partners, and cross-functional stakeholders to deliver robust solutions at scale. Within AWS Networking the NPD (Network Product Development) organization is responsible for, designing the hardware, building the software, and owning the interconnects for the routers that power the global AWS network.
NewEvening Packaging Test Engineer (Swing Shift) Ryzen SolutionsEvening Packaging Test Engineer (Swing Shift)San Jose, CAThis hands-on role involves analyzing data and ensuring project accuracy and quality through effective communication and documentation. The ideal candidate will hold a B.S. degree in a relevant field and have 2-5 years of laboratory experience.
Lab Packaging Test Engineer I Engineer In Training (Swing Shift) Ryzen SolutionsLab Packaging Test Engineer I Engineer In Training (Swing Shift)San Jose, CA$66,560Perform testing duties within the designated workday hours according to requirements to ensure customer objectives are met through proactive communication, documentation, and customer service. Maintain responsive customer communication in email and in person regarding testing services provided, test status, updates, and results.
Lab Packaging Test Engineer I Engineer In Training (Swing Shift) Artech LLCLab Packaging Test Engineer I Engineer In Training (Swing Shift)San Jose, CA$66,560–$70,720 / yearPerform testing duties within the designated workday hours according to requirements to ensure customer objectives are met through proactive communication, documentation, and customer service. Maintain responsive customer communication in email and in person regarding testing services provided, test status, updates, and results.
NewPrincipal IC Packaging & FEA Engineer LumilensPrincipal IC Packaging & FEA EngineerSan Jose, CAThe ideal candidate will possess a Bachelor's in Mechanical Engineering or related field and have extensive experience with FEA tools and advanced packaging technologies. A technology startup in San Jose is seeking an experienced IC Package Mechanical FEA Engineer to develop high-performance packaging solutions for advanced ASICs.
Manufacturing Design Engineer (MDE) - Packaging Apple IncManufacturing Design Engineer (MDE) - PackagingCupertino, CADevelop innovative solutions that enable Apple's Product and Environmental goals, including but not limited to manufacturability of fiber-based designs, lowering Apple's environmental footprint, and developing world class manufacturing solutions. (domestic and international up to 30%) A team player who is self-motived, defining and closing all engineering tasks to meet project objective, detailed oriented to cut to the root of problems, and ability to learn quickly with limited information or support.
NewSenior R&D Engineer, Advanced Packaging & SIP Broadcom CorporationSenior R&D Engineer, Advanced Packaging & SIPSan Jose, CAWith a focus on collaboration with design and validation teams, this role requires extensive experience and the ability to manage complex projects. Broadcom in San Jose is looking for an expert in advanced packaging technology to lead R&D efforts for semiconductor assembly.
Engineering Program Manager, Packaging Apple IncEngineering Program Manager, PackagingCupertino, CAThis role provides an opportunity to work with a world-class team to deliver high-quality, first-class products at scale, ensuring a memorable and delightful introduction to Apple products. Collaborate and facilitate communication across engineering managers, operations managers, marketing managers, and our OEM partners to meet aggressive cost, schedule, and quality goals.
NewThermal Solutions Engineer for SoC/CPU/GPU Packaging Advanced Micro DevicesThermal Solutions Engineer for SoC/CPU/GPU PackagingSan Jose, CAAdvanced Micro Devices, Inc is seeking a Mechanical Engineer to develop advanced thermal-mechanical solutions for SoC, CPU, and GPU products. The ideal candidate should possess strong analytical skills and CAD proficiency, with an educational background in Mechanical Engineering or a related field.
NewPackaging Electrical Engineer Intern - Automation SCN BestCoPackaging Electrical Engineer Intern - AutomationSanta Cruz, CASCN BestCo in Santa Cruz, California, is seeking a Packaging Electrical Engineer Intern to assist with troubleshooting and supporting various engineering operations. The intern will work closely with engineering teams to improve automation and control systems while gaining valuable insights into production processes.
Director, Pricing and Packaging Strategy McAfee, LLCDirector, Pricing and Packaging StrategySan Jose, CaliforniaFull timeReporting to the Head of Pricing and partnering closely with executive leaders across Marketing, Retention, Product, and Retail, you’ll set the vision and frameworks that govern how we price, package, and promote across every channel and stage of the customer lifecycle – from acquisition through renewal – ensuring strategic coherence while maximizing long-term value. You’ll lead a high-impact pricing function, influence executive decisions on monetization strategy, and shape how millions of customers experience McAfee – from the first marketing touchpoint, through product packaging, into renewals and win-back, and across our retail ecosystem.
NewSenior ASIC Packaging & SI/PI Engineer (2.5D) CiscoSenior ASIC Packaging & SI/PI Engineer (2.5D)San Jose, CACisco Systems, Inc. is looking for a Signal and Power Integrity Engineer to be part of their advanced ASIC team in San Jose, CA. Successful candidates will have a Bachelor's degree in Electrical Engineering and a strong background in signal integrity.
NewASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid) CiscoASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)San Jose, CA$152,500–$219,200 / yearMinimum QualificationsBachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best‑of‑breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
NewSenior IC Packaging Architect Hybrid Advanced Micro DevicesSenior IC Packaging Architect HybridSan Jose, CAAdvanced Micro Devices in San Jose, California is seeking an advanced packaging technology leader responsible for driving packaging architecture across products. The ideal candidate will have a proven track record in semiconductor technology development, excellent communication skills, and a strong educational background in relevant fields.
NewIntegrated Circuit Packaging Architect Advanced Micro DevicesIntegrated Circuit Packaging ArchitectSan Jose, CAResponsibilities Work with product architects in early definition stage to understand and define package architectures, roadmapLead new package technology development initiatives from concept to full technology qualificationDrive Test vehicle design and manufacturing to establish design rules, DFM/DFY guidelinesEstablish Yield roadmap and lead implementation of yield, data analytic tools as needPreferred Experience Experience in semiconductor technology development roleExperience working with manufacturing partners such as suppliers, OSATs and foundry partners. In-depth knowledge in material science, thin film process development, and/or packagingExperience in a leadership role driving cross-functional teamsProven track record of driving yield improvement, defect reduction in semiconductor fab or packaging environmentEducation BS/MS/PhD in Material Science, Mechanical Engineering, Computer Science, Applied Mathematics, Electrical Engineering or equivalentThis role is not eligible for visa sponsorship.#LI-HYBRID#LI-AP1Benefits offered are described: AMD benefits at a glance.
NewIC Packaging Architect - Lead New Package Tech & Yield Advanced Micro DevicesIC Packaging Architect - Lead New Package Tech & YieldSan Jose, CAAdvanced Micro Devices in San Jose, California, is seeking an experienced leader in packaging technology to drive architecture initiatives across multiple product lines. The ideal candidate will lead cross-functional teams in developing advanced packaging solutions while maintaining world-class communication with stakeholders.
Packaging Utility Worker Threshold Enterprises LtdPackaging Utility WorkerCASummary of Job Duties: Responsibility for this position include, assisting with the following processes: set-up, bottle filling, cotton and desiccant insertion, and capping, labeling, and packing of filled bottles. Complete all documentation required for packaging in a cGMP compliant manner, including: Packaging batch records (Travelers), box labels, room and equipment cleaning logbooks, and in-process documentation.
Packaging Utility Worker (2nd Shift) Threshold Enterprises LtdPackaging Utility Worker (2nd Shift)CASummary of Job Duties: Responsibility for this position include, assisting with the following processes: set-up, bottle filling, cotton and desiccant insertion, and capping, labeling, and packing of filled bottles. Complete all documentation required for packaging in a cGMP compliant manner, including: Packaging batch records (Travelers), box labels, room and equipment cleaning logbooks, and in-process documentation.
NewRemote Senior ASIC Packaging & SI/PI Lead CiscoRemote Senior ASIC Packaging & SI/PI LeadSan Jose, CARemoteIn this role, you will engage in design reviews, mentor junior engineers, and collaborate with cross-functional teams to deliver high-quality solutions. The ideal candidate will have extensive experience in developing high-performance ASIC packaging and be adept in high-speed design principles.
Nutrition, Food Science and Packaging Lecturer Pool California State UniversityNutrition, Food Science and Packaging Lecturer PoolCA$5,507–$5,959Lecturers are responsible for effective curriculum preparation and teaching of courses in alignment with our Department's vision and mission and the focus on applied research and serving multicultural populations, syllabus and accessibility compliance, review and grading of assignments and work, holding office hours, texts and readings, overall support of student learning and professional development, and working collaboratively with faculty and staff to promote student success. Demonstrated working knowledge of the trends in the nutrition profession in the context of diversity and globalization, including specializations with certain cultural and/or language groups; Ability to teach in online and in-person formats; Proficiency with computers, software, and technology; Experience with multimedia and social media relevant to teaching.
Packaging Architect MediaTek IncPackaging ArchitectSan Jose, CAThe ideal candidate will play a key role in identifying the optimal package architecture and key packaging technologies, establishing 3rd party relationships, communicating with partners and addressing challenges in areas such as 2.5D/3D/3.5D and System technology optimization with advanced Si nodes, including but not limited to CoWoS-S/R/L, EMIB/EMIB-T, SoIC, HBM, FCBGA, and HBPOP. Perform a trade-off analysis across silicon layout, die-to-die connectivity options, and package design/technology, evaluating their impact on key product metrics, including performance, cost, manufacturability, power efficiency, and form factor.
Semiconductor Operations - Advanced SiP Packaging Apple IncSemiconductor Operations - Advanced SiP PackagingCupertino, CAMS/BS in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, or related technical discipline Understanding of SPC, DOE, FMEA, JMP or equivalent data analysis tools, and factory quality metrics used to monitor production performance. Strong understanding of reliability testing and failure mechanisms such as temperature cycling, board-level reliability, MSL, bHAST, CAF, warpage, solder fatigue, and substrate/material interactions.
Packaging Technical Leader Cisco SystemsPackaging Technical LeaderSan Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $168,800.00 - $277,400.00 Non-Metro New York state & Washington state: $148,800.00 - $248,200.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Minimum Qualifications: * 6+ years of progressive industry experience in Semiconductor Packaging or Photonic packaging or Assembly process development or integration, with demonstrable track record of technical leadership and successful project execution.
Sr Director, Power Packaging & Module Development onsemiSr Director, Power Packaging & Module DevelopmentSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. Products include power and signal management, logic, discrete, and custom devices for automotive, communications, computing, consumer, industrial, LED lighting, medical, military/aerospace and power applications.
Director Product Line Management (Co Packaging Optical Solution) LumilensDirector Product Line Management (Co Packaging Optical Solution)San Jose, CaliforniaM.S. in Electrical Engineering, Photonics, Physics, Materials Science, or related field, or equivalent experience in photonics reliability engineering with direct exposure to Optical system, Silicon Photonics, laser technologies, and optical transceivers. Drive and support with cross-functional teams including Photonics Design, HW design, Packaging, Manufacturing, Quality Engineering, Product Marketing and Supply Chain to ensure robust product development and transfer to production.
Packaging / Production Supervisor Saputo IncPackaging / Production SupervisorCA$71,805–$92,000 / yearYou are best suited for this role if you: • Bachelors in Dairy Science, Food Science, or a related field; one to three years of supervisory experience in a food production environment; or equivalent combination of education and experience • Working knowledge of computer programs (i.e. Excel, Word, etc.) • Ability to define programs, collect data, establish facts and draw valid conclusions • Ability to lead, influence and motivate people • Ability to understand cost containment and budgetary principles • Ability to effectively communicate verbally and in writing • Ability to work flexible hours • Ability to work in a team environment as well as independently with good time management and organizational skills. We Support and Care For Our Employees By Providing Them With: • Development opportunities that enhance their career fulfillment • Meaningful compensation & benefits that help them care for their families • Opportunities to contribute to your community and enhance the lives of others through Saputo products.
NewDirector of Packaging Engineering - Consumer Electronics Shanghai BSF Human Resources Co.Director of Packaging Engineering - Consumer ElectronicsSan Jose, CAThis role involves technical management, project leadership, and strategic planning while requiring relocation to China for long-term commitment.#J-18808-Ljbffr. A recruitment firm is seeking a Head of Consumer Electronics Packaging Engineering to lead process improvement and technology implementation.
Package Architect - Advanced Packaging & System Exploration Micron Technology IncPackage Architect - Advanced Packaging & System ExplorationSan Jose, CA$177,000–$387,000 / yearResponsibilities: Define and explore advanced package architectures for future memory systems Perform package‑level trade‑off studies across SI, PI, thermals, cost, and scalability Create hands‑on package designs and models for early feasibility analysis Run SI/PI and thermal simulations and translate results into architecture guidance Define package requirements and act as extension architecture and engineering Minimum Qualifications: Bachelor's degree or equivalent practical experience in EE, ME, Materials, or related field 10+ years of hands‑on experience in package design or package‑level simulation Strong experience with package SI modeling and analysis Ability to independently build models and drive conclusions Preferred Qualifications: Master's degree in a related technical field Experience supporting architecture or pre‑silicon exploration teams Familiarity with system‑level co‑design across silicon, package, and board Experience with multi‑die or heterogeneous integration The US base salary range that Micron Technology estimates it could pay for this full-time position is: $177,000.00 - $387,000.00 a year Additional compensation may include benefits, bonuses and equity. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
NewASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote) CiscoASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)San Jose, CARemote$183,800–$263,600 / yearCisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best‑of‑breed silicon from Top of Rack (TOR) switches all the way through web‑scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Minimum QualificationsBachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.