Asic Design Efficiency Engineer NvidiaAsic Design Efficiency EngineerSanta Clara, CAThis position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms.
Rust Software Engineering Intern (Chip Design Tools) - Fall 2026 Fab2Rust Software Engineering Intern (Chip Design Tools) - Fall 2026San Francisco, CaliforniaThe people who have done well on this team tend to come from deep, rich applications: tools and engine programmers, people who have built game level editors, DAWs, CAD tools, rendering pipelines, or software where the hard problems live in the seams between data, rendering, and input. There is also plenty nearby as the application grows: a plugin system built on sandboxed WebAssembly components, a scripting API where a script is the same first-class client as the mouse, and integrations that send finished designs to the fab.
Senior Circuit Design Engineer NvidiaSenior Circuit Design EngineerSanta Clara, CAMore recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Senior Asic Design Verification Infrastructure And Tools Engineer - GPU NvidiaSenior Asic Design Verification Infrastructure And Tools Engineer - GPUSanta Clara, CAThis position offers the opportunity to have a big impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence to self-driving cars and supercomputers. NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams.
Senior Design Engineer, Coherent High Speed Interconnect NvidiaSenior Design Engineer, Coherent High Speed InterconnectSanta Clara, CAThe NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Senior Mask Design Engineer - Hardware NvidiaSenior Mask Design Engineer - HardwareSanta Clara, CAWhat you'll be doing: Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation chiplet interface projects.
Senior SRAM Circuit Design Engineer NVIDIA CorpSenior SRAM Circuit Design EngineerSanta Clara, CAGuiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications. SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
Security System Design and Configuration Specialist - Active Clearance Required Lawrence Livermore National LaboratorySecurity System Design and Configuration Specialist - Active Clearance RequiredLivermore, CA$129,150–$196,476 / yearThe scope of work within the S&P Systems Engineering section will include providing technical and operational support for the Enterprise Assets Management (EAM) project, including coordination of physical security system equipment inventory, procurements, vendor and contract activities, distribution, obsolescence planning, and depot inventory support across NNSA enterprise sites. Responsibilities include developing CAD and fabrication drawings, maintaining system design files and configuration documentation for complex security systems, leading hardware distribution efforts, and coordinating with technical staff, customers, procurement personnel, vendors, and site stakeholders to ensure effective execution of project and operational objectives.
FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncFPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$123,100–$196,900 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Sr. Design Verification Engineer Credo Semiconductor, Inc.Sr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Senior Engineer, GPU RTL Design - Pixel Pipe Samsung Electronics America IncSenior Engineer, GPU RTL Design - Pixel PipeSan Jose, CA$139,000–$208,400 / yearYou support technical excellence by driving design quality and accuracy, developing clean, synthesizable RTL, and collaborating with verification teams to enable thorough validation, resolve functional issues, and ensure coverage, robustness, and sustainability across complex graphics processing flows. In this mid-to-senior individual contributor role, you will collaborate closely with hardware and software design teams and work across multiple GPU functional domains-including control, datapath, memory systems, and fixed-function logic, with a focus on pixel processing and graphics pipeline stages.
NewDesign Engineer Aditi ConsultingDesign EngineerSunnyvale, CA$82–$85 / hourConsent to Communication and Use of AI Technology: By submitting your application for this position and providing your email address(es) and/or phone number(s), you consent to receive text (SMS), email, and/or voice communication whether automated (including auto telephone dialing systems or automatic text messaging systems), pre-recorded, AI-assisted, or individually initiated from Aditi Consulting, our agents, representatives, or affiliates at the phone number and/or email address you have provided. Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
NewDesign Engineer III eTeam Inc.Design Engineer IIISunnyvale, CAPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams. About the role: Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
Senior Mixed Signal Design Validation Engineer NvidiaSenior Mixed Signal Design Validation EngineerSanta Clara, CAAs a member of our Mixed Signal Design Validation team, you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation of electro-optical transceivers. More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.
Asic Design Engineer NvidiaAsic Design EngineerSanta Clara, CAWhat you'll be doing: Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications. Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
Mixed Signal Design Validation Engineer NvidiaMixed Signal Design Validation EngineerSanta Clara, CAAs a member of our Mixed Signal Design Validation team, you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation of electro-optical transceivers. More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.
ASIC Design Engineer NVIDIA CorpASIC Design EngineerSanta Clara, CAWhat you'll be doing: Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications. Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
Principal Modem PHY IP Design Verification Engineer - Terawave Blue Origin Enterprises LPPrincipal Modem PHY IP Design Verification Engineer - TerawaveCA$269,175–$376,843.95 / yearand/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
Principal Design Engineer DustPhotonics LtdPrincipal Design EngineerSan Jose, CA$140,000–$230,000 / yearThe ideal candidate brings deep expertise in computing and communication systems -including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink - and understands how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform.
NewSoftware Engineer, Silicon Design Methodology OpenAI LLCSoftware Engineer, Silicon Design MethodologySan Francisco, CAFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. We're looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence.