Staff SoC Design Engineer Waymo LLCStaff SoC Design EngineerMountain View, CA$251,000–$310,000 / yearYou will: Define the architecture and microarchitecture for Waymo''s next-generation autonomous vehicle SoCs, translating system-level requirements into detailed hardware specifications and RTL implementation, using your knowledge of how hardware, firmware, drivers, and compilers interact. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes.
Senior Asic Design Engineer Cornelis NetworksSenior Asic Design EngineerSan Jose, CARemoteCornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
Digital/RTL IC Design Engineer Omni Design Technologies IncDigital/RTL IC Design EngineerMilpitas, CAJob responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies. We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design's IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
Senior Digital/Mixed-Signal IC Design Engineer Omni Design Technologies IncSenior Digital/Mixed-Signal IC Design EngineerMilpitas, CAJob responsibilities include development and verification of the digital controller for high performance data converters, behavioral modeling, customer support, and to assist with synthesis and place-and-route flow for the digital controller for high performance data converters. We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Omni Design's IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
Principal/Senior Staff/Staff GPGPU Design Engineer SQL PagerPrincipal/Senior Staff/Staff GPGPU Design EngineerSan Francisco, CaliforniaNice to have Prior experience of a GPU functional blocks, including Caches• Knowledge in various DNN networks and their core ASIC implementations• Knowledge of Graphics/Compute APIs, such as CUDA/OpenCL• Knowledge of OS, software/hardware interface• Finite Precision Analysis of multi-layer compute processing pipeline. In-depth Knowledge of one of the parallel processing hardware architectures Neural Network Computation Flow on GPU/NPU Array/Vector/Systolic Processors SIMD/SIMT Processing Pipelines Base Jump manycore GPU cache hierarch and Latency-hiding with NoC Inter-connect bus fabric.
Senior Digital Design Engineer SQL PagerSenior Digital Design EngineerSan Jose, CaliforniaHands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug. Preferred Qualifications: Hands on design experience in PCIe logical / link / transaction layers.
Digital Design Engineer SQL PagerDigital Design EngineerSan Jose, CaliforniaHands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug. Preferred Qualifications: Hands on design experience in PCIe logical / link / transaction layers.
Digital Design Engineer HPDigital Design EngineerSan Francisco, California$107,400–$155,700 / yearAs a member of the team, you'll have the opportunity to contribute across the digital design process, develop your craft alongside experienced designers and engineers, and help create new interfaces, interactions, and experiences that shape our product roadmap. We’re especially interested in candidates who have experience or demonstrated interest in any of the following areas: High-fidelity prototyping using code or tools such as Origami Studio, SwiftUI, WebGL, JavaScript, or CSS.
Director of Design (UI/UX + Brand) Gantri Inc.Director of Design (UI/UX + Brand)San Francisco, CA$190,000–$220,000 / yearWe're looking for a Director of Design to lead brand design, UI/UX, and creative at Gantri - someone with exceptional taste and a track record of building cohesive, elevated brand experiences for design-forward, tech-enabled consumer companies. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information.
Senior Staff Engineer, GPU Design Verification (Formal Verification) Samsung Electronics America IncSenior Staff Engineer, GPU Design Verification (Formal Verification)San Jose, CA$198,200–$297,200 / yearYou help drive complex debug analysis and root-cause resolution by analyzing formal failures, tracing counterexamples, and collaborating closely with design and architecture teams to ensure verification aligns with architectural intent and improve design robustness. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.
Senior Staff Engineer, GPU Design Verification (Subsystems) Samsung Electronics America IncSenior Staff Engineer, GPU Design Verification (Subsystems)San Jose, CA$180,200–$247,700 / yearYou design, develop, and maintain scalable verification testbenches using SystemVerilog, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex block and subsystem behaviors. You ensure functional and performance excellence across subsystem coverage by help advancing verification methodologies, tools, and automation to improve efficiency and quality, while creating targeted and scalable test scenarios that stress interactions across multiple blocks, interfaces, and data paths within the subsystem.
Senior GPU Design Verification Engineer (GCDV) Samsung Electronics America IncSenior GPU Design Verification Engineer (GCDV)San Jose, CA$124,000–$208,400 / yearYou ensure functional and performance excellence at top level for all graphic blocks by advancing verification methodologies, tools, and automation to improve efficiency and quality, maintain technical documents, and create sophisticated test scenarios that stress full graphics pipelines (including command processing, front-end, shader cores, rasterization, and fixed-function units), covering corner cases, performance-sensitive paths, and real-world workloads. You help develop and maintain scalable verification testbenches using SystemVerilog and C++, developing test code in parallel with RTL, and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex graphics and compute behavior.
RTL Design / Microarchitecture Engineer Bolt GraphicsRTL Design / Microarchitecture EngineerSunnyvale, CaliforniaBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Digital Design RTL Engineer Broadcom CorporationDigital Design RTL EngineerSan Jose, CAJob Description: The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization, clock domain crossing (CDC) analysis and Reset Domain crossing (RDC). Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques.
Lead Asic Design Engineer Broadcom CorporationLead Asic Design EngineerSan Jose, CA$143,800–$230,000 / yearRTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
R&D Digital Design Engineer Broadcom CorporationR&D Digital Design EngineerSan Jose, CAWe are looking for a motivated and astute individual to join our team as a logic design engineer.as a logic design engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant rtl for implementing components of complex networking asics. Job Description: The core switch group (csg) at broadcom focused on developing high-performance ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks.
Design Technology Director MBH ArchitectsDesign Technology DirectorAlameda, CaliforniaBIM & Delivery Lifecycle: Experience leading complex, multi-discipline BIM coordination, writing BIM Execution Plans (BEPs), and managing large-scale model exchanges across senior stakeholders. Through integrated services (architecture, environmental graphics, fixture and interior design), we deliver world-class projects, including multi-family housing, labs, retail experiences for iconic brands, and many more.
PCB Design Layout Engineer NVIDIA CorpPCB Design Layout EngineerSanta Clara, CAWhat you'll be doing: Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (Data Center, GPU Desktop, Notebook, Automotive, Professional, Deep Learning, and AI). We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing.
AI Silicon, Junior Digital Design Engineer Unconventional AIAI Silicon, Junior Digital Design EngineerPalo Alto, CAWe are looking for accomplished and highly motivated individuals with a strong understanding of SOC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets.
Member of Technical Staff - Analog Design Unconventional AIMember of Technical Staff - Analog DesignPalo Alto, CALayout Supervision: Define detailed floorplans and critical layout guidelines for high-performance blocks, and work closely with layout engineers to ensure optimal parasitic, matching, and signal integrity performance. Mixed-Signal Integration: Collaborate with digital design teams to define interfaces, conduct top-level mixed-signal simulation, and ensure seamless integration of analog and digital blocks.