Sr. Design Verification Engineer DustPhotonics LtdSr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Staff RFIC Design Engineer Western Digital CorpStaff RFIC Design EngineerSan Jose, CAResponsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide.
NewCore Engineering - Design Engineer III Artech LLCCore Engineering - Design Engineer IIISunnyvale, CA$80–$86.66 / hourPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feedback to design/power-modeling teams. We are seeking a Power Measurement Design Verification Engineer to develop and execute DV test strategies focused on power and performance characterization at the IP and SoC level.
Designer III, Interior Architecture & Design Ware MalcombDesigner III, Interior Architecture & DesignCAEstablished in 1972, Ware Malcomb is a dynamic, forward-thinking commercial real estate design firm providing professional architecture, interior design, civil engineering, branding, building measurement, structural engineering and MEP engineering services to clients throughout the world. You will support project execution through Design Development (DD), Construction Documents (CD), and Contract Administration (CA), including submittals and furniture selection, while mentoring junior team members and coordinating project efforts under the general direction of a licensed interior designer.
SerDes Circuit Design Engineer Apple IncSerDes Circuit Design EngineerCupertino, CAYou will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA). Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
DDR Design Engineer Apple IncDDR Design EngineerCupertino, CAAs a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Principal Digital Design Engineer Astera LabsPrincipal Digital Design EngineerSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAWorking closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the designs intended behavior is fully exercised. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.
Designer II, Interior Architecture & Design Ware MalcombDesigner II, Interior Architecture & DesignPleasanton, CAEstablished in 1972, Ware Malcomb is a dynamic, forward-thinking commercial real estate design firm providing professional architecture, interior design, civil engineering, branding, building measurement, structural engineering and MEP engineering services to clients throughout the world. The firm is also ranked among the top 10 Architecture/Engineering firms in Engineering News-Record's Top 500 Design Firms and the Top 30 Interior Design Firms in Interior Design magazine's Top 100 Giants.
NewHardware Design Engineer - PCB Layout General MotorsHardware Design Engineer - PCB LayoutSunnyvale, CA$98,300–$177,800 / yearThe ECU hardware design team's mission is to ensure our products are designed to target the growing needs of our customers while ensuring robust, well-designed hardware which meets GM specifications and testing requirements from early hardware through the production design. The Role: In-vehicle electronics is a fast-growing technology in the global automotive industry featuring many cutting-edge technologies such as Compute, body controllers, multi-view cameras, Gig+Ethernet, PCIe, digital/analog interfaces and more.
Design Verification Engineer - SoC EtchedDesign Verification Engineer - SoCSan Jose, CaliforniaBacked by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads.
Architect - FPGA Design, AXI/ UCIe Protocol Synopsys IncArchitect - FPGA Design, AXI/ UCIe ProtocolSunnyvale, CAThis team builds the critical bridge between Synopsys' ZeBu emulation and HAPS prototyping platforms and the real-world devices, testers, and hosts that customers need to connect to their pre-silicon designs. The team works closely with IP teams developing PCIe, CXL, UCIe, and other high-speed protocols, as well as with emulation and prototyping platform engineers to deliver integrated system-level validation solutions.
Design Verification Engineer - Internal IP EtchedDesign Verification Engineer - Internal IPSan Jose, CaliforniaBacked by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready.
Principle Design Engineer (ADC expertise) Monolithic Power SystemsPrinciple Design Engineer (ADC expertise)San Jose, CaliforniaAs a Principal design engineer, you will be responsible for the full cycle of our high-resolution ADC products, from architecture to design, simulation, layout supervision and post-layout verification. Self-motivated , willing to learn new technologies, & capable of working effectively within a group of individuals across multiple disciplines.
NewDesign Verification Engineer MythicDesign Verification EngineerPalo Alto, CA$120,000–$225,000 / yearBecause today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Design Verification Engineer - SoC Etched.ai IncDesign Verification Engineer - SoCSan Jose, CARequirements You may be a good fit if you have: • ASIC/SoC Design & Verification Experience • Strong understanding of digital design, RTL, and ASIC design flows • Hands-on experience with performance verification, simulation, and modeling • SystemVerilog & Python Expertise • Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog • Skilled in writing Python scripts for automation, data analysis, and performance modeling • Architecture & Performance Modeling Knowledge • Experience building and maintaining performance models for chip subsystems • Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators • Software Performance Profiling • Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning • Some exposure to kernel level performance metrics and profiling tools. Key Responsibilities As a DV Engineer (Systems/Performance) owning the verification of a certain area of performance features in an ASIC design, you will have responsibilities as follows: • Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Silicon Design Verification Engineer, Quantum AI GoogleSilicon Design Verification Engineer, Quantum AIMountain View, CAFull timeYou will work as part of a team of digital, DV, physical design, and radio frequency/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Goleta, CA, USA.Minimum qualifications: Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience.
Principal Engineer - Digital ASIC Design Microchip Technology IncPrincipal Engineer - Digital ASIC DesignSan Jose, CA$70,304–$163,000 / yearOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.
Physical Design Engineer II Silicon Engineering Space Exploration Technologies CorpPhysical Design Engineer II Silicon EngineeringSunnyvale, CA$155,000–$185,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.