Standard Cell Design Lead Substrate IncStandard Cell Design LeadSan Francisco, CA$150,000–$275,000 / yearThis role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen Americas technological leadership.
Digital Design Engineer SQL PagerDigital Design EngineerSan Jose, CaliforniaHands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug. Preferred Qualifications: Hands on design experience in PCIe logical / link / transaction layers.
NewSenior Manager - Analog Design Advanced Micro Devices IncSenior Manager - Analog DesignSanta Clara, CAThe focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, equalization; and development of abstracted models for link performance simulations. Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features.
Director of Design (UI/UX + Brand) Gantri Inc.Director of Design (UI/UX + Brand)San Francisco, CA$190,000–$220,000 / yearWe're looking for a Director of Design to lead brand design, UI/UX, and creative at Gantri - someone with exceptional taste and a track record of building cohesive, elevated brand experiences for design-forward, tech-enabled consumer companies. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information.
Senior Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Senior Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Sr Principal Design Engineer CadenceSr Principal Design EngineerSan Jose, CA$154,000–$286,000 / yearYou will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D - develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers' most complex architectural and high-Speed Protocol challenges. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence's market-leading hardware emulation and FPGA prototyping platforms.
MTS Digital Design Engineer onsemiMTS Digital Design EngineerSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure.
Senior FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncSenior FPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$154,900–$247,800 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncFPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
CPU Core Design Verification Testbench Lead TenstorrentCPU Core Design Verification Testbench LeadSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. How Tenstorrent applies AI across the DV lifecycle - from test planning and stimulus through regression debug, triage, and coverage analysis - using workflows designed to keep context tight and outputs auditable.
Senior Design Verification Engineer AuradineSenior Design Verification EngineerSanta Clara, CA$200,000–$300,000 / yearYou will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture-from individual RTL blocks to complete HW/SW systems running real-world workloads.
CPU Core Design Verification Testbench Lead Tenstorrent IncCPU Core Design Verification Testbench LeadSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. How Tenstorrent applies AI across the DV lifecycle - from test planning and stimulus through regression debug, triage, and coverage analysis - using workflows designed to keep context tight and outputs auditable.
Sr. Staff/Staff Engineer, Digital Design InnoPhase IoTSr. Staff/Staff Engineer, Digital DesignSan Jose, CAIf you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find your playground at Innophase IoT. In addition to delivering high quality digital solutions, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing.
Senior Design Engineer (MOSFET / IGBT) Alpha & Omega SemiconductorSenior Design Engineer (MOSFET / IGBT)Sunnyvale, CAFull timeAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. Primary job functions include:Power device structure and process simulation with TCAD tools including Tsuprem4, Medici, and SentaurusDevice characterization with LCR meter, curve tracer, FET test, etc.
AutoCAD Design/Drafter Auriga CorporationAutoCAD Design/DrafterMilpitas, CaliforniaAURIGA JOB POSTING (Auriga Website: www.aurigacorp.com ) Auriga Corporation was established in 1990, to provide high-quality design, engineering and project management services for Electric Power, Telecommunication and Information Technology systems. Auriga Corporation continues to provide Consulting Services to the Rail and Transit Systems, Municipal Utilities, United States Federal Government, The State of California, International Governments and International Public and Private Sector Organizations.
FPGA Design Engineer - Avionics E-SpaceFPGA Design Engineer - AvionicsSaratoga, CAOur team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
RFIC Design Engineer , Amazon Leo Amazon.com IncRFIC Design Engineer , Amazon LeoSunnyvale, CAExplore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs. Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Kuiper customers.
Senior CAD Engineer, RTL Design, Silicon, Google Cloud Google LLCSenior CAD Engineer, RTL Design, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
RTL Design Engineer, Machine Learning Accelerators Google LLCRTL Design Engineer, Machine Learning AcceleratorsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Careers Skip navigation links home Home Homework_outlinework_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in.