Recreation Specialist II, PT (Continuous) City of Oakland, CaliforniaRecreation Specialist II, PT (Continuous)Oakland, CA$30.37–$37.28 / hourDo you have any experience with Performing Arts such as: (Ballet, Tap, Modern, Hip Hop, Turf,, Ballroom, African, Chicago Stepping, Belly Dance, etc.), Singers, Song Writers, Musicians, Conductors (for Civic orchestra and Community Orchestra), Drama,, Educational Theater, Stage Rigging, Stage Lighting & Sound, Film Makers, Videographers, Audio Engineers, Music Producers, Photographers, etc. Do you have any experience in Arts such as: Ceramics, Sculpture, Painting and Drawing, Textile Arts, Print Making, Metal Jewelry, Black and White and Digital Photography, Coding, Graphic Arts, Videography, Glass Making (Fused Glass, Stained Glass, and Flamework Beadmaking, etc.), or Woodworking?.
Technical Architect Skidmore Owings & MerrillTechnical ArchitectSan Francisco, California$100,000–$140,000 / yearLeads the team’s construction phase services scope including making periodic site visits tomonitor construction progress and identifying areas needing correction and/or modification;attending visual and performance mockup review; and reviewing shop drawings for design intent. Together with the Senior Designer, Project Manager, and/or Project Architect, the Technical Designer is the day-to-day co-leader of the project in all project phases, with significant responsibilities in the Design Development through Construction Administration phases.
CPU Processor Power Management Verification Engineer Apple IncCPU Processor Power Management Verification EngineerSanta Clara, CAWrite assertions and apply formal verification to the designMinimum BS and 10+ years of relevant industry experience Experience in digital logic, micro-processor architecture, or power management architecture Experience with digital design verification including Verilog/System-Verilog based testbenches and transactors checkers Experience with design verification environments like random constraint verification or UVM base testbenches Programming skills in Perl or PythonMaster's degree preferred In depth knowledge of power management architecture and design techniques Experience in system Verilog assertions or silicon bringup or UPF and low power simulation Experience with advanced verification techniques such as formal verification Advanced programming skills such as object orientated programming or CPU assembly language is a plus Ability to independently come up with design verification testbenches and environments and solve complex design verification problems Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design. As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows: Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic.
Senior Electrical Engineer - Compute Hardware Applied Intuition IncSenior Electrical Engineer - Compute HardwareSunnyvale, CA$140,000–$220,000 / yearAt Applied Intuition, you will: Design electrical schematics for automotive, off-road, and defense (optional) applications, incorporating SoCs/MCUs, power (SMPS, Linear), memory components (eMMC, DDR, NVMe), and peripherals from concept to production. Applied Intuition is headquartered in Sunnyvale, California, with offices in Washington, D.C. San Diego; Ft. Walton Beach, Florida; Ann Arbor, Michigan; London; Stuttgart; Munich; Stockholm; Bangalore; Seoul; and Tokyo.
Principal Platform Security Architect NeurophosPrincipal Platform Security ArchitectSan Mateo, CaliforniaHyperscale customers will not deploy an accelerator they cannot verify, so this position owns the machinery that makes our silicon verifiable: the root of trust, secure and measured boot, device attestation, signed firmware update, and security telemetry. The ideal candidate has shipped these subsystems on real silicon, can speak fluently to both RTL designers and firmware engineers, and knows the datacenter compliance landscape well enough to design toward it rather than retrofit for it.
Electrical Engineer Applied Intuition IncElectrical EngineerSunnyvale, CA$113,800–$184,697 / yearAt Applied Intuition, you will: Design electrical schematics for automotive, off-road, and defense (optional) applications, incorporating SoCs/MCUs, power (SMPS, Linear), memory components (eMMC, DDR, NVMe), and peripherals from concept to production. Applied Intuition is headquartered in Sunnyvale, California, with offices in Washington, D.C. San Diego; Ft. Walton Beach, Florida; Ann Arbor, Michigan; London; Stuttgart; Munich; Stockholm; Bangalore; Seoul; and Tokyo.
Senior SoC Power Analysis & Optimization Engineer MatXSenior SoC Power Analysis & Optimization EngineerMountain View, CaliforniaSupport to Parents: Up to 12 weeks paid parental leave regardless of path to parenthood, 10 weeks pregnancy disability leave, flexible return-to-work hours, and Benepass reproductive health & parental benefit. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI.
Product Manager Web (AEM) Solutions Stamford American International HospitalProduct Manager Web (AEM) SolutionsPalo Alto, CA$55.85–$74 / hourRequires technical expertise to translate institutional needs into platform-viable specifications; works with business stakeholders to develop a complete understanding of requirements for new features and/or enhancements to meet website users unmet needs. This is a role for someone who sees stewardship as equally important as innovation—who can balance technical feasibility, user-centric design, and institutional discipline to ensure our website system remains coherent, compliant, and scalable as both uniform and tailored work continue to grow.
Design Staff Atelier TenDesign StaffSan Francisco, CaliforniaWe’re an innovative multidisciplinary firm of environmental design consultants, building services engineers and lighting designers focused on delivering high-quality, award-winning building services and sustainable design within the built environment sector. Collaborate Atelier Ten’s integrated design groups to support the full range of our services, which include environmental design consulting, daylight and façade analysis, carbon analysis design and benchmarking.
VP, Product Design, Informatica Tableau SoftwareVP, Product Design, InformaticaRedwood City, CADevelop and articulate a compelling design vision shaped by design thinking principles — emphasizing empathy, ideation, prototyping, and testing — and use experience, credibility, and strategic insight to inspire bold ideas and drive transformative outcomes across the organization and broader Salesforce ecosystem. Strategic Vision & Leadership: • Build a culture of customer obsession by embedding it into every facet of design strategy — championing a deep understanding of real user problems and fostering innovation and customer-centered thinking across the team.
Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Senior Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Sr Principal Design Engineer CadenceSr Principal Design EngineerSan Jose, CA$154,000–$286,000 / yearYou will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D - develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers' most complex architectural and high-Speed Protocol challenges. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence's market-leading hardware emulation and FPGA prototyping platforms.
MTS Digital Design Engineer onsemiMTS Digital Design EngineerSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure.
FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncFPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$123,100–$196,900 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
CPU Core Design Verification Testbench Lead Tenstorrent IncCPU Core Design Verification Testbench LeadSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. How Tenstorrent applies AI across the DV lifecycle - from test planning and stimulus through regression debug, triage, and coverage analysis - using workflows designed to keep context tight and outputs auditable.
Design Verification Engineer Broadcom CorporationDesign Verification EngineerSan Jose, CA$120,000–$192,000 / year2) Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems. 3) Developing verification environments including testbenches and verification API's associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains.
Design Engineer - Flow Development Broadcom CorporationDesign Engineer - Flow DevelopmentSan Jose, CAThe candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. Our group's mission is to provide an advanced timing sign-off flow to Broadcom's chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
NVIDIA 2027 Internships: Hardware Design for Test (DFT) NVIDIA CorpNVIDIA 2027 Internships: Hardware Design for Test (DFT)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.